(1) Field of the Invention
The invention relates to a method of trench etching in the fabrication of integrated circuits, and more particularly, to a method of trench etching where the trenches are sized down from the design mask size by etching in the manufacture of integrated circuits.
(2) Description of the Prior Art
Damascene and dual damascene processes have become a future trend in metallization. Trenches or vias and trenches are etched in an insulating layer. The trenches or vias and trenches are inlaid with metal to complete the contacts. In order to reduce RC delay to a minimum, low dielectric constant materials (k less than 3) are preferably used as the insulating layer. Trenches or vias and trenches are etched through the low-k film typically using a photoresist mask. At present, ion metal plasma (IMP) can successfully coat a thin film of about 300 Angstroms on the sidewall of a 0.24 xcexcm trench having a 2000 Angstrom top side thickness. Assuming that the overhang percentage of the IMP layer is 5%, this may pose a problem as the trench size shrinks to 0.15 xcexcm or lower. It may not be possible to coat a uniform sidewall thin film for subsequent electrochemical plating processes, for example.
U.S. Pat. No. 6,114,250 to Ellingboe et al and U.S. Pat. No. 6,096,655 to Lee et al teach a via etch through a low-k film using a hard mask. U.S. Pat. No. 6,165,898 to Jang et al discloses a dual-damascene etch using a hard mask. U.S. Pat. No. 4,729,815 to Leung shows a via etch using a hard mask where the via has a gentle slope. U.S. Pat. No. 5,843,846 to Nguyen et al shows an etch to form rounded corners.
A principal object of the present invention is to provide an effective and very manufacturable method of etching trenches in the fabrication of integrated circuit devices.
Another object of the invention is to provide a method of etching trenches through a low dielectric constant material layer in the fabrication of integrated circuit devices.
Yet another object of the invention is to provide a method of etching trenches through a low-k material layer using a hard mask.
A further object of the invention is to provide a method of etching trenches through a low-k material layer using a hard mask wherein the trenches are sized down from the mask size by etching.
Yet another object of the invention is to provide a method of etching trenches through a low-k material layer using a hard mask wherein the trenches are sized down from the mask size by etching without sacrificing a vertical trench profile.
In accordance with the objects of this invention a method of etching trenches through a low-k material layer using a hard mask wherein the trenches are sized down from the mask size by etching without sacrificing a vertical trench profile is achieved. A low-k dielectric material is provided over a region to be contacted on a substrate. A hard mask layer is deposited overlying the dielectric material. A mask is formed over the hard mask layer wherein the mask has a first opening of a first width. A second opening is etched in the hard mask layer where it is exposed by the mask wherein the second opening has a second width smaller than the first width and wherein the second opening has inwardly sloping sidewalls. A trench is etched through the dielectric layer to the region to be contacted through the second opening whereby the trench has a width equal to the second width. The trench is filled with a metal layer to complete fabrication of the integrated circuit device.